Yongseok Lee
Logic Design Engineer at Samsung Electronics
Suwon-si, South Korea
Summary
👤
Senior🎓
Top SchoolYongseok Lee is a Logic Design Engineer at Samsung Electronics with 11 years of experience blending formal verification and RTL design for NAND Flash systems. He began his career in formal and static verification—authoring property-based assertions and static checks for NAND Flash and RISC-V–based MCU components—and has translated that verification-first mindset into RTL development since 2025. Proficient in SystemVerilog/Verilog, Questa Formal, JasperGold, VC SpyGlass CDC and industry simulators, he focuses on building clean, efficient, and production-ready logic with strong automation skills in Python and Tcl. Based in Suwon, South Korea, he aims to be a well-rounded digital designer who reduces silicon risk by integrating verification rigor early in the design cycle. An uncommon strength is his mechanical engineering background from Seoul National University, which gives him a systems-oriented perspective on hardware design trade-offs.
10 years of coding experience
2 years of employment as a software developer
Bachelor of Science - BS, Mechanical Engineering / System Semiconductor Engineering for AI, Bachelor of Science - BS, Mechanical Engineering / System Semiconductor Engineering for AI at 서울대학교 (Seoul National University)대전과학고등학교
Github Skills (31)
jssc9
android-things9
rxtx8
jar7
reactivity7
modbus-tcp7
hosting7
react6
nodejs6
libmodbus6
java6
modbus5
grid5
excel5
treegrid5
Programming languages (4)
Github contributions (5)
yongseokleecom/docker-yona
May 2016 - Mar 2019
Contributions:67 commits, 79 pushes, 3 branches in 2 years 11 months
naoohcom/naoohcom.github.io
Sep 2017 - May 2021
Contributions:8 pushes, 1 branch in 3 years 8 months
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