Summary
Yu-chuan Chuang is a Silicon Architect with a Ph.D. and nine years’ experience specializing in digital ASIC/RTL/IP design, AI/ML hardware, and computer architecture. He has led tapeouts of energy- and area-efficient DNN accelerators and ML engines in 40nm processes, achieving multi-fold improvements in TOPS/W and area-energy efficiency and publishing in top conferences. His work spans industry and academia—from senior CPU power engineering at MediaTek to research collaborations at Georgia Tech where he applied Transformer-based models to automate accelerator design space exploration. Skilled at coordinating cross-functional teams, he has secured large-scale AI funding and mentored student researchers to multiple journal and conference publications and awards. Now based in Taiwan and working at Google, he combines hands-on silicon implementation experience with ML-driven hardware optimization, often blurring the line between algorithm and architecture.
9 years of coding experience
5 years of employment as a software developer
Phd, Electronics Engineering, Phd, Electronics Engineering at National Taiwan University
English, Chinese, Mandarin