Summary
Yu G is a hardware engineer with 11 years of experience designing and validating system-level hardware for high-performance ASICs and rack systems, currently supporting MatX AI ASIC hardware and racks in San Francisco. He has led evaluation board design, bring-up, and certification testing across companies including Marvell and Innovium, with hands-on expertise in schematic/layout, thermal/mechanical considerations, and system architecture (clock, power, interfaces). Comfortable bridging hardware and software, Yu writes low-level tools and automation (PMBus voltage control, test scripts) and favors C and Java from his computer engineering background. He excels at translating complex technical issues for customers and cross-functional teams, often guiding schematic/layout decisions and production scaling. Result- and quality-driven with an easygoing style, he routinely pursues new hardware and software skills outside of work. A practical problem-solver, Yu’s blend of ASIC system experience and software fluency makes him effective at taking designs from schematic through certification and field support.
11 years of coding experience
10 years of employment as a software developer
University of California Santa Cruz
English, chinese (mandarin & cantonese)