Yu Hung
Senior Design Verification Engineer
Taiwan
Summary
👤
Senior🎓
Top SchoolYu Hung is a Senior Design Verification Engineer based in Taiwan with eight years of cross-disciplinary experience in IP and firmware verification, specializing in DisplayPort, USB4, AMBA VIP integration, and RAL model automation. He combines deep C/C++ and Python skills with SystemVerilog and FPGA bring-up experience to close the loop between firmware and silicon verification, having automated RAL model generation and unified assertion/coverage control to improve DV efficiency. Past roles include firmware verification for embedded controllers and driver bring-up (OpenOCD contributions) as well as full-stack and field application engineering where he applied scripting to cut workloads by 30%. Yu holds a master's focus in data science and intelligent networks from National Taiwan University and has an unusual background in air traffic control, which informs his systems-thinking approach to complex verification flows. Currently developing in-house VIPs and actively gearing skills toward telematics internships, he blends practical engineering with process improvements that reduce manual effort and accelerate time-to-closure.
8 years of coding experience
3 years of employment as a software developer
Bachelor's degree, Air Traffic Controller, Bachelor's degree, Air Traffic Controller at 國立臺灣海洋大學碩士, 電機與通訊工程研究所 - 資料科學與智慧網路組, 碩士, 電機與通訊工程研究所 - 資料科學與智慧網路組 at 國立臺灣大學Exchange program, business administration, GPA 3.5/4.0, Exchange program, business administration, GPA 3.5/4.0 at 廈門大學
Chinese, English
Github Skills (3)
python8
speech1
deep-learning1
Programming languages (3)
Github contributions (5)
oceanchad/Python-for-everybody
Jan 2018 - Mar 2019
Contributions:48 commits, 40 pushes, 1 branch in 1 year 1 month
oceanchad/ychong
Aug 2018 - Apr 2021
Contributions:51 pushes, 1 branch in 2 years 8 months
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