Yueh-ting Chen
Senior Architect at NVIDIA
New Taipei, Taiwan
Summary
🤩
Rockstar🎓
Top SchoolYueh-ting Chen is a Senior Architect at NVIDIA with nine years of experience in compiler engineering, ASIC tooling, and low-level system optimization. He previously worked at SiFive and Skymizer, focusing on compiler backends and lowering ML models to custom silicon, and contributed to NTU’s campus-wide systems early in his career. An active open-source contributor, he has improved RISC-V ISA simulator Spike by simplifying and optimizing vector and shifting instructions, demonstrating deep familiarity with RISC-V semantics and performance-focused code changes. Based in New Taipei, Taiwan, he blends research-driven rigor with production engineering, and brings a pragmatic focus on code clarity and efficiency that often surfaces in refinements rather than big rewrites. His GitHub motto—“Go go change the world!”—captures his drive to make incremental technical improvements that scale.
9 years of coding experience
4 years of employment as a software developer
Bachelor's degree Computer Science & Information Engineering, Bachelor's degree Computer Science & Information Engineering at National Taiwan University
French, Russian, Chinese, English, Hokkien, Japanese
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (14)
c1710
vector10
risc-v10
code-optimization10
assembly10
c-language10
c1110
cprogramming-language10
emulation10
vectordb10
assemble10
qemu10
assembler10
virtualization10
Programming languages (12)
Github contributions (5)
riscv-software-src/riscv-isa-sim
Nov 2021 - Jan 2022
Spike, a RISC-V ISA Simulator
Role in this project:
Back-end Developer
Back-end DeveloperContributions:22 commits, 18 PRs, 9 comments in 2 months
Contributions summary:Yueh-ting contributed to the RISC-V ISA simulator by simplifying and optimizing various vector instructions. Their work included simplifying `vmulhsu` and averaging add/subtract operations by modifying header files and instruction implementations. The user also eliminated redundant parameters in narrowing integer right-shift instructions, improving code clarity and efficiency. They demonstrate a strong understanding of RISC-V architecture and low-level code optimization.
risc-visariscvriscv32simulator
riscv/rvv-intrinsic-doc
Jan 2023 - Jan 2023
Contributions:3 commits in 8 days
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