Yuichi Sugiyama
Security Researcher at 株式会社Ikotas Labs
Tokyo, Japan
Summary
🤩
Rockstar🎓
Top SchoolYuichi Sugiyama is a security researcher and engineer based in Tokyo with a decade of experience spanning hardware design, embedded systems, and security research. He has worked across startups and established firms—contributing to projects from RISC-V microarchitecture (implementing set-associative DCache changes and low-level fixes) to security roles at Ricerca and Mercari—bridging silicon-level engineering with practical security evaluation. He holds advanced degrees from the University of Tokyo and a background in information intelligence from Kobe University, reflecting strong academic grounding in information science. Known for hands-on low-level problem solving, he moves fluidly between RTL/hardware verification and software-centric security work. He also co-leads Ikotas Labs as COO, signaling a shift into operational and leadership responsibilities while retaining deep technical contribution. Colleagues describe him as a pragmatic engineer who surfaces subtle hardware bugs that have outsized impact on system correctness and security.
9 years of coding experience
3 years of employment as a software developer
博士（情報科学）, 博士（情報科学） at 東京大学工学部, 情報知能工学科, 工学部, 情報知能工学科 at 神戸大学
Github Skills (11)
risc-v10
caching10
embedded10
vivado10
systemverilog10
sys10
digital-design9
makefile9
simulations9
simulation9
test-automation8
Programming languages (10)
Github contributions (5)
rsd-devel/rsd
Dec 2019 - Dec 2020
RSD: RISC-V Out-of-Order Superscalar Processor
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:33 commits, 5 PRs, 18 pushes in 1 year
Contributions summary:Yuichi's primary contributions involve modifying and updating the DCache module within the RSD RISC-V processor project. These changes include implementing set-associative cache functionality, refactoring NRU connections, and fixing bugs related to initialization and latch generation. The user's work demonstrates a focus on low-level hardware design and optimization, specifically targeting the data cache component. Additionally, the user modified test drivers and makefiles for Vivado simulation.
risc-vasicout-of-orderriscsuperscalar
mmxsrup/libsha1
Dec 2018 - Jan 2021
Contributions:3 commits, 2 pushes, 1 branch in 2 years 1 month
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