Yunsup Lee
Chief Technology Officer at SiFive
San Francisco Bay Area United States
Summary
🤩
Rockstar🎓
Top SchoolYunsup Lee is a seasoned technology leader and CTO with 15 years of experience building and scaling RISC-V hardware and software ecosystems from the lab to production. Based in the San Francisco Bay Area, he combines deep academic rigor (PhD/MS from UC Berkeley) with hands-on contributions to cornerstone open-source projects such as Rocket Chip, Spike, and the RISC-V proxy kernel, where he’s implemented instruction formats, simulator enhancements, and opcode fixes. As former chair of the RISC-V Technical Steering Committee and a long-time SiFive executive, he uniquely bridges processor microarchitecture, toolchain integration, and systems software. His work shows a persistent focus on verification and performance—adding targeted tests, benchmarks, and hwacha support—that reflects an engineer who moves complex ISA features into reliable silicon and simulator tooling.
15 years of coding experience
11 years of employment as a software developer
PhD Computer Science, PhD Computer Science at University of California, BerkeleyBS Computer Science Electrical Engineering, BS Computer Science Electrical Engineering at Korea Advanced Institute of Science and Technology
Github Skills (29)
verilog10
assembly10
c-language10
computer-architecture10
testing10
risc-v10
cpu-architecture10
test-framework10
c-programming10
vectordb10
vector10
kernel10
microarchitecture10
kernel-mode10
assemble10
Programming languages (9)
Github contributions (5)
riscv-software-src/riscv-isa-sim
Jul 2010 - Mar 2017
Spike, a RISC-V ISA Simulator
Role in this project:
Backend Developer
Backend DeveloperContributions:79 commits, 5 pushes, 1 branch in 6 years 9 months
Contributions summary:Yunsup primarily contributed to the RISC-V ISA simulator, focusing on enhancements to the application link and the implementation of the tohost/fromhost communication mechanism. They introduced fixes to the simulator's interaction with the front-end server (fesvr) and addressed issues related to stdint.h, ensuring compatibility. The user also modified the processor's interaction with the memory model.
risc-visariscvriscv32simulator
chipsalliance/rocket-chip
Dec 2011 - Nov 2017
Rocket Chip Generator
Role in this project:Back-end Developer
Back-end DeveloperContributions:464 commits, 93 PRs, 159 pushes in 6 years
Contributions summary:Yunsup implemented new instruction formats and performed initial integration for vector unit (VU) components within the Rocket Chip Generator. Their work involved modifying code, specifically in the area of control logic and datapath, to incorporate new instructions and features related to the VU. Further contributions involved establishing connections with memory, along with implementing a new interface for the vector unit.
rtlriscvchipchiselscala
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