Yves Teissier
Senior Embedded Software Engineer at ITC
Le Versoud, Auvergne-Rhône-Alpes, France
Summary
👤
Senior🎓
Top SchoolYves Teissier is a Senior Embedded Software Engineer and system architect with 12+ years designing safety-critical and real-time systems across semiconductor, energy, and automotive domains. He blends deep C/C++ and Fractal-C experience with SysML/UML model-driven design, RTOS/Linux-RT architectures, and formal/safety-oriented tooling (Krono-safe, PsyC, Method-B) to deliver SIL-rated and deterministic solutions. Yves has driven firmware and architecture work on SoCs (AM64, STM32), TSN/EtherCAT realtime networking, and electric vehicle charging systems while mentoring junior engineers. His background in semiconductor component characterization and early career device-driver work gives him an uncommon hardware-aware perspective that informs robust embedded software and system-level tradeoffs.
12 years of coding experience
24 years of employment as a software developer
DESS electronic components, DESS electronic components at université montpellier II5 Semiconductor components, 5 Semiconductor components at Université de Rennes (France)
English
Github Skills (10)
macros3
compile3
backend3
annotations2
optimization2
compile-time2
code-generation2
metadata2
footprint2
compiler1
Github contributions (2)
StephaneSeyvoz/Optimization-Backend
Feb 2014 - Jun 2014
Contributions:24 commits in 3 months
optimizationscode-generationmacroscompile-timeannotations
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