Zeeshan Rafique
CPU Verification Engineer
Barcelona, Catalonia, Spain
Summary
👤
Senior🎓
Top SchoolZeeshan Rafique is a CPU Verification Engineer based in Barcelona with 8 years of hands-on experience in RISC-V microarchitecture and hardware verification. He has driven ISA and coherence validation for out-of-order RISC-V cores—achieving 94% ISA coverage—by building UVM testbenches, generating assembly tests, and automating CI with Python. His background spans tapeout experience on SKY130 (Azadi-SoC via Google Open-MPW), FPGA-based emulation on AWS, and contributions to award-winning open projects like the SERV core MDU integration. Comfortable across research and industry, he blends low-level RTL work, multi-core coherency debugging, and system-level test automation. Colleagues rely on him for turning complex decoder and instruction-set features into robust regression suites that scale across nightly and weekly pipelines.
8 years of coding experience
2 years of employment as a software developer
Electrical Engineering, Computer Systems Engineering, Electrical Engineering, Computer Systems Engineering at Usman Institute of Technology
Urdu, English, Spanish
Stackoverflow
31reputation
167reached
0answers
2questions
Github Skills (98)
verilog10
fixed-point10
intro10
asic10
risc10
soc10
6800010
32-bit10
fpga10
cpu10
bit10
deterministic10
shieldsio9
computer-engineering9
silicon9
Programming languages (11)
Github contributions (5)
merledu/azadi-soc
Aug 2021 - Nov 2022
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
Contributions:2 releases, 14 reviews, 124 commits in 1 year 2 months
ibexsystemverilogbitcomputer-engineeringopenembedded
merledu/Buraq-compressed-assembler
Apr 2020 - Sep 2021
This is the compressed assembler for RISC-V.
Contributions:11 commits, 3 PRs, 4 pushes in 1 year 5 months
risc-vrisccompressedassembler
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