Zeger Van De Vannet
ASIC FPGA Design And Validation Engineer
Ghent Metropolitan Area Belgium
Summary
🤩
Rockstar🎓
Top SchoolZeger Van De Vannet is an ASIC/FPGA Design and Validation Engineer with 12 years of experience, currently applying his expertise at Nokia from Ghent. He blends hardware design and validation know-how with practical software skills, contributing to open-source projects like Nuitka (improving cross-platform Python compilation) and nvim-treesitter (enhancing Verilog parsing, folding, and scoping). His background in electrical and electronic engineering (Universiteit Gent) underpins a methodical approach to complex SoC and FPGA verification challenges. Colleagues know him for bridging the gap between low-level hardware behavior and developer tooling, ensuring designs are both robust and developer-friendly.
12 years of coding experience
Master of Science in Engineering, Electrical and electronic engineering, Master of Science in Engineering, Electrical and electronic engineering at Universiteit Gent
Github Skills (20)
verilog10
tree-sitter10
python10
packaging10
msys10
packing10
neovim10
compiler-compiler10
parsing10
parse10
package10
compile10
compiler10
syntax-highlighting10
performance-analysis8
Programming languages (19)
Github contributions (5)
nvim-treesitter/nvim-treesitter
Nov 2020 - Sep 2022
Nvim Treesitter configurations and abstraction layer
Role in this project:
Software Engineer (focused on language tooling)
Software Engineer (focused on language tooling)Contributions:5 reviews, 6 commits, 4 PRs in 1 year 10 months
Contributions summary:Zeger primarily contributed to the Verilog language support within the nvim-treesitter project. Their work focused on improving syntax highlighting, adding features like folding, and implementing local variable scoping. The user also addressed missing keywords and updated the version information related to Verilog, enhancing the overall functionality of the language parsing. This included modifying queries to define code folding, scope definition, and syntax highlighting rules for the Verilog language.
nvim-treesitterluatreesittertree-sittervim
Nuitka/Nuitka
May 2021 - Nov 2021
Nuitka is a Python compiler written in Python. It's fully compatible with Python 2.6, 2.7, 3.4-3.13. You feed it your Python app, it does a lot of clever things, and spits out an executable or extension module.
Role in this project:Back-end Developer
Back-end DeveloperContributions:6 commits, 3 PRs, 12 comments in 5 months
Contributions summary:Zeger contributed to the Nuitka compiler, focusing on improving its compatibility with various Python modules and environments. The contributions primarily involve adding implicit imports for dependencies like `gi.overrides` and supporting the copy of typelib files needed by GI modules. Additionally, the user made changes to normalize paths within the build system to ensure consistency across different operating systems, particularly MSYS2. These changes help ensure the portability and proper functioning of the compiled Python applications.
python-2-6packaging-toolpythonpython-applot
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