Zhangxiaowen Gong
Research Scientist at Intel Labs
Fremont, California, United States
Summary
👤
Senior🎓
Top SchoolZhangxiaowen Gong is a research scientist at Intel Labs' Parallel Computing Lab with nine years of experience in computer architecture and compiler-aware optimization for DNNs on shared-memory machines. He earned his PhD from UIUC under Prof. Josep Torrellas, where his thesis and publications (including a MICRO 2020 paper) advanced sparsity-aware hardware and software techniques for training and inference. His background blends rigorous academic research with industry impact from internships at Qualcomm and Apple, where he delivered practical tools and ML-driven performance models. Known for designing a novel vector processing unit prototype validated in cycle-level simulation, he combines simulator-driven architecture design with compiler and systems expertise. Based in Fremont, CA, he brings a track record of turning theoretical insights into validated architectural designs that improve DNN efficiency on CPUs.
9 years of coding experience
8 years of employment as a software developer
University of Illinois Urbana-Champaign
Chinese, English
Stackoverflow
21reputation
119reached
0answers
1question
Github Skills (26)
openmp10
x86-6410
cpp10
opencl9
tbb9
deep-learning9
oneapi9
sycl8
deep-neural-networks8
neural-network7
qtcreator6
qnetworkaccessmanager6
qt6
cycle5
timing5
Programming languages (1)
Github contributions (5)
andygongyb/SparseTrainTests
Mar 2019 - May 2019
Contributions:9 pushes, 1 branch in 1 month
uiuc-cumf/cumf_als
May 2017 - May 2017
Contributions:7 pushes in 6 days
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