Zhengrong Wang
Postdoctoral Researcher at UCLA
Los Angeles, California, United States
Summary
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Rockstar🎓
Top SchoolZhengrong Wang is a postdoctoral researcher and PhD candidate-turned-researcher at UCLA with 11 years of experience at the intersection of computer architecture and systems software. He brings hands-on engineering from internships at NVIDIA and Facebook to academic research, contributing practical fixes and improvements to the widely used gem5 computer-system simulator (including x86 ISA and Ruby memory-system fixes). His background spans electrical engineering at Tsinghua and exchange study at ETH Zürich, complemented by deep graduate training in computer science at UCLA. Comfortable shipping low-level simulator and CPU-related fixes, he blends rigorous research with production-oriented debugging and performance tuning. An early-career researcher with industry experience, he often translates complex architectural problems into reliable, maintainable simulator code.
11 years of coding experience
6 years of employment as a software developer
Bachelor’s Degree Electrical and Electronics Engineering, Bachelor’s Degree Electrical and Electronics Engineering at Tsinghua UniversityUniversity of California, Los AngelesExchange Student Electrical Electronic and Communications Engineering Technology/Technician, Exchange Student Electrical Electronic and Communications Engineering Technology/Technician at ETH Zürich
English, German
Github Skills (12)
simulations10
simulation10
memory-management10
c-language10
cprogramming-language10
architectures10
simulator10
modeling10
architecture10
x8610
risc-v9
python8
Programming languages (3)
Github contributions (5)
gem5/gem5
Nov 2019 - Feb 2022
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
Back-end Developer
Back-end DeveloperContributions:1 review, 5 commits, 2 PRs in 2 years 3 months
Contributions summary:Zhengrong's contributions primarily involve fixing and improving the gem5 simulator. They corrected issues related to x86 instruction set architecture, specifically handling floating-point control words and address computations. They also addressed bugs and made improvements to the Ruby memory system, including renaming a prefetcher and correcting type casting issues. Additionally, the user fixed a CPU-related bug regarding resetting group statistics and updated the simulation configurations to ensure proper thread creation.
storedsimulationupstreamsimulatorgem5-simulator
seanzw/yart-cpp
Aug 2015 - Aug 2018
Contributions:88 commits, 82 pushes, 4 branches in 3 years
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