Zhimeng Li
Design Verification Engineer
Raleigh, North Carolina, United States
Summary
👤
Senior🎓
Top SchoolZhimeng Li is a Design Verification Engineer with eight years of hands-on experience in RTL logic design, verification, synthesis, and timing analysis for ASIC/SoC projects. Based in Raleigh, NC and trained in nanoelectronics and photonics (M.S., NCSU; B.S., Nankai), he combines strong Verilog and Synopsys toolchain skills with working knowledge of SystemVerilog/UVM, C++, TCL and Perl. At Analog Devices he applies practical EDA flow expertise and a fundamentals-first understanding of high-performance processor design and chip integration. Earlier roles in optical testing and laser systems sharpened his experimental rigor and data-driven troubleshooting approach. Detail-oriented and organized, he is comfortable translating specifications into synthesizable RTL and verifiable testbenches while collaborating across teams. An unusual strength is his cross-domain background bridging photonics hardware testing and digital verification, which helps him reason about signal integrity and system-level interactions.
8 years of coding experience
Master of Science (M.S.), Nanoelectronics and Photonics, Master of Science (M.S.), Nanoelectronics and Photonics at North Carolina State UniversityBachelor of Science (B.S.), Nanotechnology and photonics, Bachelor of Science (B.S.), Nanotechnology and photonics at Nankai University
Github Skills (3)
computer-science8
counting5
java4
Programming languages (3)
Github contributions (5)
leezhimeng919/blog
Jun 2019 - Dec 2019
Contributions:176 commits, 132 pushes, 1 branch in 6 months
leezhimeng919/Learning-Notes
Sep 2017 - Jul 2019
大学期间的学习笔记
Contributions:59 pushes, 1 branch in 1 year 9 months
java
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