Summary
周耀阳 is a PhD candidate with 11 years of hands-on experience in computer architecture, specializing in performance analysis, CPUs, and the interplay between large language models and data-structure-aware systems (LLM DSA). He blends deep academic research with practical performance engineering, focusing on squeezing efficiency from hardware and software stacks. Known to balance rigorous experimentation with real-world constraints, he often surfaces actionable insights that improve throughput and latency. Outside research, he is a husband and father, which informs his pragmatic, long-term approach to problem solving.
11 years of coding experience