Zhuang Wu

Senior Engineer at NVIDIA

California, United States
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Summary

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Senior
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Top School
Zhuang Wu is a senior engineer based in California with eight years of deep experience in RTL and system-level design for GPUs and ASICs, currently modeling GPU functions and leading chip bring-up at NVIDIA. He blends C++ GPU modeling, SystemVerilog RTL design, and formal verification (Jasper/VC Formal) to deliver silicon from Day 0 to product, with prior roles spanning NVLink/NVSwitch ASICs, PCIe root complex microarchitecture, and FPGA acceleration for neural nets. His background includes implementing a Wavenet FPGA accelerator at Alibaba's DAMO Research Lab and building high-performance compression and InfiniBand FPGA projects at Sun Microsystems, reflecting a strong cross-domain hardware-software skillset. A USC M.S. in Electrical Engineering (4.0) underpins his rigorous approach to algorithmic and architectural optimizations for FPGA/ASIC targets. Notably, he navigates both high-level algorithm mapping and low-level verification nuances, making him effective at closing the gap between research prototypes and production silicon.
code8 years of coding experience
job6 years of employment as a software developer
bookMaster's Degree, Electrical Engineering, 4.0, Master's Degree, Electrical Engineering, 4.0 at University of Southern California
languagesEnglish, Chinese
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Stackoverflow

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Github Skills (13)

websocket8
hessian8
redis8
high-performance8
netty7
grpc7
rpc6
queue3
rocketmq2
message-queue2
golang2
kafka2
distributed-systems1

Programming languages (1)

Java

Github contributions (5)

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wuzhuang5-zz/algorithm

Jul 2019 - May 2020

Contributions:108 commits in 9 months
wuzhuang5-zz/summer-rpc

Jul 2018 - Apr 2020

🚀 high performance rpc framework
Contributions:118 commits in 1 year 9 months
rpcredisgrpcrpc-frameworkwebsocket
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