Zhuang Wu is a senior engineer based in California with eight years of deep experience in RTL and system-level design for GPUs and ASICs, currently modeling GPU functions and leading chip bring-up at NVIDIA. He blends C++ GPU modeling, SystemVerilog RTL design, and formal verification (Jasper/VC Formal) to deliver silicon from Day 0 to product, with prior roles spanning NVLink/NVSwitch ASICs, PCIe root complex microarchitecture, and FPGA acceleration for neural nets. His background includes implementing a Wavenet FPGA accelerator at Alibaba's DAMO Research Lab and building high-performance compression and InfiniBand FPGA projects at Sun Microsystems, reflecting a strong cross-domain hardware-software skillset. A USC M.S. in Electrical Engineering (4.0) underpins his rigorous approach to algorithmic and architectural optimizations for FPGA/ASIC targets. Notably, he navigates both high-level algorithm mapping and low-level verification nuances, making him effective at closing the gap between research prototypes and production silicon.
8 years of coding experience
6 years of employment as a software developer
Master's Degree, Electrical Engineering, 4.0, Master's Degree, Electrical Engineering, 4.0 at University of Southern California
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.